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ST10F268 Scheda tecnica(PDF) 71 Page - STMicroelectronics

Il numero della parte ST10F268
Spiegazioni elettronici  16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM
PDF  74 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F268 Scheda tecnica(HTML) 71 Page - STMicroelectronics

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ST10F168
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20.5.13 - External Bus Arbitration
VDD = 5V ± 10%, VSS = 0V, for Q6 version : TA = -40, +85°C and for Q3 version TA = -40, +125°C, CL = 100pF,
unless otherwise specified.
Note: 1. Partially tested, guaranted by design characterization.
Notes: 1. The ST10F168 will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pullup) after t64.
Symbol
Parameter
Max. CPU Clock
25MHz
Variable CPU Clock
1/2 TCL = 1 to 25MHz
Unit
Minimum
Maximum
Minimum
Maximum
t61 SR HOLD input setup time to CLKOUT
20
–
20
–
ns
t62 CC CLKOUT to HLDA high or BREQ low delay
–
20
–
20
ns
t63 CC CLKOUT to HLDA low or BREQ high delay
–
20
–
20
ns
t64 CC CSx release
1
–
20
–
20
ns
t65 CC CSx drive
-4
24
-4
24
ns
t66 CC Other signals release
1
–
20
–
20
ns
t67 CC Other signals drive
-4
24
-4
24
ns
Figure 30 : External bus arbitration, releasing the bus
t61
t63
t66
1)
t64
1)
2)
t62
3)
CLKOUT
HOLD
HLDA
BREQ
Others
CSx
(P6.x)



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