ST14C02C datasheet(8/12 Pages) STMICROELECTRONICS

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ST14C02C

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Figure 9. Read Mode Sequences

DEV SEL *

BYTE ADDR

DEV SEL

DATA OUT 1

AI01942

DATA OUT N

CURRENT

ADDRESS

READ

DEV SEL

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

DATA OUT

SEQUENTIAL

CURRENT

READ

DATA OUT N

DEV SEL *

BYTE ADDR

SEQUENTIAL

RANDOM

READ

DEV SEL *

DATA OUT 1

ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

Sequential Read

This mode can be initiated with either a Current

Address Read or a Random Address Read. How-

ever, in this case the master

does acknowledge

the data byte output, and the memory continues to

output the next byte in sequence. To terminate the

stream of bytes, the master must

not acknowledge

the last byte output, and

must generate a STOP

condition. The output data comes from consecu-

tive byte addresses, with the internal byte address

counter automatically incremented after each byte

output. After the last memory address, the address

counter will ‘roll-over’ and the memory will contin-

ue to output data from the start of the memory

block.

Acknowledge in Read Mode

In all read modes the memory waits for an ac-

knowledgment during the 9th bit time. If the master

does not pull the SDA line low during this time, the

memory device terminates the data transfer and

switches to its standby state.

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