DEV SEL *

BYTE ADDR

DEV SEL

DATA OUT 1

AI00794C

DATA OUT N

CURRENT

ADDRESS

READ

DEV SEL

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

DATA OUT

SEQUENTIAL

CURRENT

READ

DATA OUT N

DEV SEL *

BYTE ADDR

SEQUENTIAL

RANDOM

READ

DEV SEL *

DATA OUT 1

ACK

R/W

NO ACK

ACK

R/W

ACK

ACK

R/W

ACK

ACK

ACK

NO ACK

R/W

NO ACK

ACK

ACK

R/W

ACK

ACK

R/W

ACK

NO ACK

Figure 11. Read Modes Sequence

Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.

put, but MUST generate a STOP condition. The

output data is from consecutive byte addresses,

with the internal byte address counter automat-

ically incremented after each byte output. After a

count of the last memory address, the address

counter will ’roll- over’ and the memory will continue

to output data.

Acknowledge in Read Mode. In all read modes

the ST24/25x16 wait for an acknowledge during the

9th bit time. If the master does not pull the SDA line

low during this time, the ST24/25x16 terminate the

data transfer and switches to a standby state.

13/17

ST24/25C16, ST24/25W16