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ST5451D Scheda tecnica(PDF) 31 Page - STMicroelectronics |
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ST5451D Scheda tecnica(HTML) 31 Page - STMicroelectronics |
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31 / 34 page ![]() DMA BUS TIMING (Reception Mode) Symbol Parameter Min. Max. Unit tACC Data Delay from ACKR 110 ns tDF Output Float Delay 25 ns tWAR Minimum width ACKR 110 ns tWAR Minimum width ACKR 70 ns tDRAR REQR Delay from ACKR 80 ns DMA BUS TIMING (Transmission Mode) Symbol Parameter Min. Max. Unit tDAS Data Setup to ACKX 35 ns tDAH Data Hold from ACKX 10 ns tWAX Minimum width ACKX 60 ns tWAX Minimum width ACKX 70 ns tDRAX REQX Delay from ACKX 80 ns Figure 19: DMA frame reception timing Figure 20: DMA frame transmission timing ST5451 31/34 |
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