ST62E40B datasheet(41/72 Pages) STMICROELECTRONICS

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ST62T40B/E40B

TIMER 1& 2 (Cont’d)

4.2.1 TIMER 1 Operating Modes

There are three operating modes, which are se-

lected by the TOUT and DOUT bits (see TSCR

two clocks which can be connected to the 7-bit

prescaler (fINT ÷ 12 or TIMER pin signal), and to

the output mode.

4.2.1.1 Gated Mode

(TOUT = “0”, DOUT = “1”)

In this mode the prescaler is decremented by the

Timer clock input (fINT ÷ 12), but ONLY when the

signal on the TIMER pin is held high (allowing

pulse width measurement). This mode is selected

by clearing the TOUT bit in the TSCR register to

“0” (i.e. as input) and setting the DOUT bit to “1”.

4.2.1.2 Event Counter Mode

(TOUT = “0”, DOUT = “0”)

In this mode, the TIMER pin is an input and the

prescaler is decremented on the rising edge.

4.2.1.3 Output Mode

(TOUT = “1”, DOUT = data out)

The TIMER pin is connected to the DOUT latch,

hence the Timer prescaler is clocked by the pres-

caler clock input (fINT ÷ 12).

The user can select the desired prescaler division

ratio through the PS2, PS1, PS0 bits. When the

TCR count reaches 0, it sets the TMZ bit in the

TSCR. The TMZ bit can be tested under program

control to perform a timer function whenever it

goes high. The low-to-high TMZ bit transition is

used to latch the DOUT bit of the TSCR and trans-

fer it to the TIMER pin. This operating mode allows

external signal generation on the TIMER pin.

Table 16. Timer Operating Modes

4.2.2 TIMER 2 Operating Mode

The Timer prescaler is clocked by the prescaler

clock input (fINT ÷ 12).

The user can select the desired prescaler division

ratio through the PS2, PS1, PS0 bits. When the

TCR count reaches 0, it sets the TMZ bit in the

TSCR. The TMZ bit can be tested under program

control to perform a timer function whenever it

goes high.

4.2.3 Timer Interrupt

When one of the counter registers decrements to

zero with the associated ETI (Enable Timer Inter-

rupt) bit set to one, an interrupt request is generat-

ed as described in Interrupt Chapter. When the

counter decrements to zero, the associated TMZ

bit in the TSCR register is set to one.

4.2.4 Application Notes

The user can select the presence of an on-chip

pull-up on the TIMER pin as option.

TMZ is set when the counter reaches zero; howev-

er, it may also be set by writing 00h in the TCR

The TMZ bit must be cleared by user software

when servicing the timer interrupt to avoid unde-

sired interrupts when leaving the interrupt service

routine. After reset, the 8-bit counter register is

loaded with 0FFh, while the 7-bit prescaler is load-

ed with 07Fh, and the TSCR register is cleared.

This means that the Timer is stopped (PSI=“0”)

and the timer interrupt is disabled.

A write to the TCR register will predominate over

the 8-bit counter decrement to 00h function, i.e. if a

write and a TCR register decrement to 00h occur

simultaneously, the write will take precedence,

and the TMZ bit is not set until the 8-bit counter

reaches 00h again. The values of the TCR and the

PSC registers can be read accurately at any time.

TOUT

DOUT

Timer Pin

Timer Function

Input

Event Counter

Input

Gated Input

Output

Output “0”

Output

Output “1”

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