ST62T52B datasheet(48/68 Pages) STMICROELECTRONICS

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ST62T52B ST62T62B/E62B

5.3 INSTRUCTION SET

The ST6 core offers a set of 40 basic instructions

which, when combined with nine addressing

modes, yield 244 usable opcodes. They can be di-

vided into six different types: load/store, arithme-

tic/logic, conditional branch, control instructions,

jump/call, and bit manipulation. The following par-

agraphs describe the different types.

All the instructions belonging to a given type are

presented in individual tables.

Load & Store. These instructions use one, two or

three bytes in relation with the addressing mode.

One operand is the Accumulator for LOAD and the

other operand is obtained from data memory us-

ing one of the addressing modes.

For Load Immediate one operand can be any of

the 256 data space bytes while the other is always

immediate data.

Table 16. Load & Store Instructions

Notes:

X,Y. Indirect Register Pointers, V & W Short Direct Registers

# .

Immediate data (stored in ROM memory)

rr.

Data space register

∆. Affected

* .

Not Affected

Instruction

Addressing Mode

Bytes

Cycles

Flags

LD A, X

Short Direct

∆

LD A, Y

Short Direct

∆

LD A, V

Short Direct

∆

LD A, W

Short Direct

∆

LD X, A

Short Direct

∆

LD Y, A

Short Direct

∆

LD V, A

Short Direct

∆

LD W, A

Short Direct

∆

LD A, rr

Direct

∆

LD rr, A

Direct

∆

LD A, (X)

Indirect

∆

LD A, (Y)

Indirect

∆

LD (X), A

Indirect

∆

LD (Y), A

Indirect

∆

LDI A, #N

Immediate

∆

LDI rr, #N

Immediate

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