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ST72622K2 Scheda tecnica(PDF) 49 Page - STMicroelectronics

Il numero della parte ST72622K2
Spiegazioni elettronici  LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI
PDF  132 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72622K2 Scheda tecnica(HTML) 49 Page - STMicroelectronics

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PWM AUTO-RELOAD TIMER (Cont’d)
PWM CONTROL REGISTER (PWMCR)
Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = Reserved.
Bit 5:4 = OE[1:0]
PWM Output Enable
These bits are set and cleared by software. They
enable or disable the PWM output channels inde-
pendently acting on the corresponding I/O pin.
0: PWM output disabled.
1: PWM output enabled.
Bit 3:2 = Reserved.
Bit 1:0 = OP[1:0]
PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the two PWM
output signals.
Notes:
– When an OPx bit is modified, the PWMx output
signal polarity is immediately reversed.
– If DCRx=FFh then the output level is always 0.
– If DCRx=00h then the output level is always 1.
DUTY CYCLE REGISTERS (DCRx)
Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = DC[7:0]
Duty Cycle Data
These bits are set and cleared by software.
A DCRx register is associated with the OCRx reg-
ister of each PWM channel to determine the sec-
ond edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARR register). These DCR registers allow
the duty cycle to be set independently for each
PWM channel.
70
00
OE1
OE0
00
OP1
OP0
PWMx output level
OPx
Counter <= OCRx
Counter > OCRx
10
0
01
1
70
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0



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