ST72E331 datasheet(16/107 Pages) STMICROELECTRONICS

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ST72E331 ST72T331

CPU REGISTERS (Cont’d)

CONDITION CODE REGISTER (CC)

Read/Write

Reset Value: 111x1xxx

The 8-bit Condition Code register contains the in-

terrupt mask and four flags representative of the

result of the instruction just executed. This register

can also be handled by the PUSH and POP in-

structions.

These bits can be individually tested and/or con-

trolled by specific instructions.

Bit 4 = H

Half carry.

This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or

ADC instruction. It is reset by hardware during the

same instructions.

0: No half carry has occurred.

1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc-

tion. The H bit is useful in BCD arithmetic subrou-

tines.

Bit 3 = I

Interrupt mask.

This bit is set by hardware when entering in inter-

rupt or by software to disable all interrupts except

the TRAP software interrupt. This bit is cleared by

software.

0: Interrupts are enabled.

1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET in-

structions and is tested by the JRM and JRNM in-

structions.

Note: Interrupts requested while I is set are

latched and can be processed when I is cleared.

By default an interrupt routine is not interruptable

because the I bit is set by hardware at the start of

the routine and reset by the IRET instruction at the

end of the routine. If the I bit is cleared by software

in the interrupt routine, pending interrupts are

serviced regardless of the priority level of the cur-

rent interrupt routine.

Bit 2 = N

Negative.

This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,

logical or data manipulation. It is a copy of the 7th

bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc-

tions.

Bit 1 = Z

Zero.

This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical

or data manipulation is zero.

0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test

instructions.

Bit 0 = C

Carry/borrow.

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instructions. It is

also affected by the “bit test and branch”, shift and

rotate instructions.

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