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ST7538

Figure 4. Packet Mode Timing

Control Register Access

The communication with ST7538 Control Register is always synchronous. The access is achieved using

the same lines of the Mains interface (RxD, TxD and CLR/T) plus REG_DATA Line.

The ST7538 sampled the TxD line on CLR/T rising edges. The control Register content is updated at the

end of the register access section (REG_DATA falling edge). If more than 24 bits are transferred to

ST7538 only the latest 24 bits are stored inside the Control Register.

RxD are stable on CLR/T rising edges MSB First.

CLR_T

IDLE

IDLE

IDLE

RXD

CLR_T

RXD

TXD

D03IN1406