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EMD12164P Scheda tecnica(PDF) 2 Page - Emerging Memory & Logic Solutions Inc |
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EMD12164P Scheda tecnica(HTML) 2 Page - Emerging Memory & Logic Solutions Inc |
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2 / 45 page ![]() 2 EMD12164P 512M: 32M x 16 Mobile DDR SDRAM Rev 0.0 Preliminary 512M : 32M x 16bit Mobile DDR SDRAM Table 1: ORDERING INFORMATION NOTE : 1. EMLSI is not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in EMLSI when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. Part No. Max Freq. Interface Package Remark EMD12164P-60(DDR332) 166 (CL3), 111 (CL2) LVCMOS Wafer Biz. EMD12164P-75(DDR266) 133 (CL3), 83 (CL2) FEATURES 1.8V power supply, 1.8V I/O power LVCMOS compatible with multiplexed address. Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe(DQS) Four banks operation. MRS cycle with address key programs. CAS latency (2, & 3). Burst length (2, 4, & 8). Burst type (Sequential & Interleave). Differential clock inputs(CK and CKB). EMRS cycle with address key programs. PASR(Partial Array Self Refresh). DS (Driver Strength) Internal auto TCSR (Temperature Compensated Self Refresh) Deep power-down(DPD) mode. DM for write masking only. Auto refresh and self refresh modes. 64 refresh period (8K cycle). Operating temperature range (-25 ~ 85 ). GENERAL DESCRIPTION This EMD12164P is 536,870,912 bits synchronous double data rate Dynamic RAM. Each 134,217,728 bits bank is organized as 8,192 rows by 1024columns by 16 bits, fabricated with EMLSI’s high performance CMOS technology. This device uses a double data rate architecture to achieve high- speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. |
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