TPS72017YZUT datasheet(2/19 Pages) TI

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ABSOLUTE MAXIMUM RATINGS

(1)

DISSIPATION RATINGS

TPS720xx

SBVS100A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION(1)

PRODUCT

VOUT

(2)

TPS720xxyyyz

XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V).

YYY is the package designator.

Z is tape and reel quantity (R = 3000, T = 250).

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2)

Output voltages from 0.9V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming;

minimum order quantities may apply. Contact factory for details and availability.

At TJ = –40°C to +125°C (unless otherwise noted). All voltages are with respect to GND.

PARAMETER

TPS720xx

UNIT

Input voltage range (steady-state), VIN

(2)

–0.3 to +5.0

Peak transient input voltage, VIN_PEAK

(3)

+5.5

Bias voltage range, VBIAS

–0.3 to +6.0

Enable voltage range, VEN

–0.3 to +6.0

Output voltage range, VOUT

–0.3 to +5.0

Peak output current, IOUT

Internally limited

Output short-circuit duration

Indefinite

Total continuous power dissipation, PDISS

See Dissipation Ratings Table

Human body model (HBM)

2000

ESD rating

Charged device model (CDM)

500

Machine model (MM)

100

Operating junction temperature range, TJ

–55 to +125

°C

Storage temperature range, TSTG

–55 to +150

°C

(1)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2)

To ensure proper operation of the device it is necessary that VIN ≤ VBIAS under all conditions.

(3)

For durations no longer than 1ms each, for a total of no more than 1000 occurrences over the lifetime of the device.

DERATING FACTOR

BOARD

PACKAGE

RθJC

RθJA

ABOVE TA = +25°C

TA < +25°C

TA = +70°C

TA = +85°C

High-K(1)

YZU

51°C/W

248°C/W

4mW/°C

403mW

222mW

160mW

(1)

The JEDEC high-K (2s2p) board used to derive this data was a 3- × 3-inch, multilayer board with 1-ounce internal power and ground

planes and 2-ounce copper traces on top and bottom of the board.

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