V54C365804VC datasheet(7/54 Pages) MOSEL

7 / 54 page

MOSEL VITELIC

V54C365804VC

V54C365804VC Rev. 0.6 September 1999

Address Input for Mode Set (Mode Register Operation)

Similar to the page mode of conventional

DRAM’s, burst read or write accesses on any col-

umn address are possible once the RAS cycle

latches the sense amplifiers. The maximum tRAS or

the refresh interval time limits the number of random

column accesses. A new burst access can be done

even before the previous burst ends. The interrupt

operation at every clock cycles is supported. When

the previous burst is interrupted, the remaining ad-

dresses are overridden by the new address with the

full burst length. An interrupt which accompanies

with an operation change from a read to a write is

possible by exploiting DQM to avoid bus contention.

When two or more

banks are activated

sequentially,

interleaved

bank

read

write

operations are possible. With the programmed

burst length, alternate access and precharge

operations on two or more banks can realize fast

serial data access modes among many different

pages. Once two or more banks are activated,

column to column interleave operation can be done

between different pages.

A11

A10 A9

Address Bus (Ax)

Burst Length

CAS Latency

Mode Register

CAS Latency

Latency

Reserve

010

011

100

Reserve

Burst Length

Length

Sequential

Interleave

000

001

010

011

Reserve

Full Page

Reserve

Burst Type

Type

Sequential

Interleave

Operation Mode

BA1 BA0 A11 A10 A9 A8 A7

Mode

0000

Burst Read/Burst

Write

0000

Burst Read/Single

Write

Operation Mode

BA0

BA1

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