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DR80390CPU Scheda tecnica(PDF) 3 Page - Digital Core Design |
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DR80390CPU Scheda tecnica(HTML) 3 Page - Digital Core Design |
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3 / 7 page ![]() All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. ● Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementa- tion. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bit- streams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. ● Single Design license for ○ VHDL, Verilog source code called HDL Source ○ Encrypted, or plain text EDIF called Netlist ● One Year license for ○ Encrypted Netlist only ● Unlimited Designs license for ○ HDL Source ○ Netlist ● Upgrade from ○ HDL Source to Netlist ○ Single Design to Unlimited Designs SYMBOL prgdatai(7:0) xramdatai(7:0) prgdatao(7:0) prgrd xramdatao(7:0) xramaddr(23:0) xramrd xramwr sfroe sfrwe sfrdatao(7:0) sfraddr(7:0) ramoe ramwe ramdatai(7:0) sfrdatai(7:0) int0 int1 clk reset ramdatao(7:0) ramaddr(7:0) stop pmm xramdataz docddatao docdclk docddatai prgwr prgaddr(23:0) prgdataz BLOCK DIAGRAM ramdatai(7:0) int0 int1 clk reset ramdatao(7:0) ALU Control Unit Interrupt Controller Opcode Decoder Program Memory Interface External Memory Interface Power Management Unit Internal Data Memory Interface User SFR Interface DoCD™ Debug Unit sfrdatai(7:0) xramdatai(7:0) prgdatai(7:0) prgaddr(23:0) docddatai docddatao docdclk prgrd xramwr xramrd xramaddr(23:0) xramdatao(7:0) ramwe ramoe sfrwe sfroe sfraddr(7:0) sfrdatao(7:0) pmm stop xramdataz ramaddr(7:0) prgwr prgdatao(7:0) prgdataz |
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