C511 datasheet(82/128 Pages) SIEMENS

82 / 128 page

On-Chip Peripheral Units

Semiconductor Group

6-49

6.4.8 Register Description

6.4.8.1

SSC Control Register SSCCON

The bit addressable register SSCCON provides the basic control of the SSC functions like general

enable/disable, mode selections and transmitter control.

Special Function Registers SSCCON (Address E8H)

Reset Value : 07H

Bit

Function

SCEN

SSC System Enable

SCEN =0 : SSC subsystem is disabled, related pins are available as general I/O.

SCEN=1 : SSC subsystem is enabled.

TEN

Slave Mode - Transmitter enable

TEN =0

: Transmitter output STO will remain in tristate state,

regardless of the state of SLS.

TEN=1 and SLS =0 : Transmitter will drive the STO output.

In master mode the transmitter will be enabled all the time, regardless of the setting

of TEN.

MSTR

Master Mode Select

MSTR=0 : Slave mode is selected

MSTR=1 : Master mode is selected

This bit has to be set to the correct value depending on the hardware setup of the

system before the SSC will be enabled. It must not be modified afterwards. There

is no on-chip support for dynamic switching between master and slave mode

operation.

CPOL

Clock Polarity

This bit controls the polarity of the shift clock and in conjunction with the CPHA bit

which clock edges are used for sample and shift.

CPOL=0 : SCLK idle state is low.

CPOL=1 : SCLK idle state is high.

SCEN

TEN

MSTR

CPOL

E8H

SSCCON

Bit No.

MSB

LSB

CPHA

BRS2

BRS1

BRS0

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