V61C518256 datasheet(2/12 Pages) MOSEL

2 / 12 page

V61C518256 Rev. 0.3 July 1998

MOSEL VITELIC

V61C518256

Pin Descriptions

A0–A14

Address Inputs

These 15 address inputs select one of the 32,768 x

8 bit segments in the RAM.

Chip Enable Inputs

CE is an active LOW input. Chip Enable must be

LOW when reading from or writing to the device.

When HIGH, the device is in standby mode with I/O

pins in the high impedance state.

Output Enable Input

The Output Enable input is active LOW. When OE

is LOW with CE LOW and WE HIGH, data of the

selected memory location will be available on the

I/O pins. When OE is HIGH, the I/O pins will be in

the high impedance state.

Write Enable Input

An active LOW input, WE input controls read and

write operations. When CE and WE inputs are both

LOW, the data present on the I/O pins will be

written into the selected memory location.

I/O0–I/O7 Data Input and Data Output Ports

These 8 bidirectional ports are used to read data

from and write data into the RAM.

VCC

Power Supply

GND

Ground

Pin Configurations (Top View)

28-Pin SOJ

28-Pin TSOP (Standard)

VCC

A11

A10

I/O0

I/O1

I/O2

GND

I/O7

I/O6

I/O5

I/O4

518256-01

A13

A14

A12

I/O3

A11

A13

VCC

A14

A12

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

518256-03

V61C518256 Scheda tecnica(PDF) 2 Page - Mosel Vitelic, Corp

V61C518256 Scheda tecnica(HTML) 2 Page - Mosel Vitelic, Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

Scheda tecnica Scarica

Link URL