Device operation

M41T00

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2.7

Characteristics

2.8

READ mode

In this mode, the master reads the M41T00 slave after setting the slave address (see

Figure 7). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the

word address An is written to the on-chip address pointer. Next the START condition and

slave address are repeated, followed by the READ mode control bit (R/W = 1). At this point,

the master transmitter becomes the master receiver. The data byte which was addressed

will be transmitted and the master receiver will send an acknowledge bit to the slave

transmitter. The address pointer is only incremented on reception of an acknowledge bit.

The M41T00 slave transmitter will now place the data byte at address An+1 on the bus. The

master receiver reads and acknowledges the new byte and the address pointer is

incremented to An+2.

This cycle of reading consecutive addresses will continue until the master receiver sends a

STOP condition to the slave transmitter.

An alternate READ mode may also be implemented, whereby the master reads the M41T00

slave without first writing to the (volatile) address pointer. The first address that is read is the

last one stored in the pointer.

Table 2.

AC characteristics

Symbol

1.

Min

Typ

Max

Units

SCL clock frequency

0

100

kHz

Clock low period

4.7

µs

Clock high period

4µs

SDA and SCL rise time

1µs

SDA and SCL fall time

300

ns

START condition hold time

(after this period the first clock pulse is generated)

4µs

START condition setup time

(only relevant for a repeated start condition)

4.7

µs

(2)

2.

Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling

edge of SCL.

Data hold time

0

ns

Data setup time

250

ns

STOP condition setup time

4.7

µs

Time the bus must be free before a new

transmission can start

4.7

µs