5/31

STLC1511

Figure 2. The block diagram of the STLC1511

3.2 Receive Path Specifications

Note: The first stage of the RxPGA provides a coarse gain of 0/20dB with a differential input or 6/26dB with a

single ended input. The second stage implements a programmable gain from 0dB to 20dB in 0.5dB steps.

12

14

B a nd ga p/

Bias Gen

14 -bit

12 -b it

AD C

DA C

4.416M

4.416M

35.328M /

5

8/4

69

2.56M /35.328M

2.56M

35.328M

(Externa l Clock M ode)

(O scillator M ode)

DI G C L K

EN B

DR X

RX IN N

RXI NP

T X SIN [1:0]

FR M C L K

R X S O U T [1:0]

C K 35M

TX O P

TX O N

FR E F

V CAP

2

2

G

OS C N E

OS C P E

OS C P B

OS C N B

DT X

90

°

DIG R E F

17.622M

RX O P IN P

RXO P I NN

+

-

2/3 /4/8

PFD

CP

+

-

G=1

fp=2M H z

fp= 2M H z

+

-

+

-+

-

Shaded blocks are only usabe when the PLL is active. Crystal based external resonator for the CPE Mode, LC

based resonator for the CO Oscillator Mode. 35.328 MHz external reference in CO External Clock Mode.