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STLC60135 Scheda tecnica(PDF) 20 Page - STMicroelectronics

Il numero della parte STLC60135
Spiegazioni elettronici  TOSCA ADSL DMT TRANSCEIVER
PDF  25 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC60135 Scheda tecnica(HTML) 20 Page - STMicroelectronics

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SLAP INTERFACE, AC Electrical Characteristics
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Tper
Clock Period
refer to MCLK
ns
Th
Clock High
11
ns
Tl
Clock Low
11
ns
Ts
Setup
3
ns
Thd
Hold
2
ns
Td
Data Delay
20pF load
3
6
ns
Analog Front End Control Interface
The Analog Front End Interface is designed to be
connected to the STLC60134 Analog Front End
component.
Transmit Interface
The 16 bit words are multiplexed on 4 AFTXD
output signals. As a result 4 cycles are needed to
transfer 1 word. Refer to table 1 for the bit/pin al-
location for the 4 cycles. The first of 4 cycles is
identified by the CLWD signal. Refer to Figure 26.
The STLC60135 fetches the 16 bit word to be
multiplexed on AFTXD from the Tx Digital Front-
End module.
Receive Interface
The 16 bit receive word is multiplexed on 4
AFRXD input signals. As a result 4 cycles are
needed to transfer 1 word. Refer to Table 2 for
the bit / pin allocation for the 4 cycles. The first of
4 cycles is identified by the CLWD must repeat
after 4 MCLK cycles.
Cycle0 Cycle1 Cycle2 Cycle3
Test0
Test1
Test2
Test3
D98TL320
MCLK
CLWD
AFTXD
AFTXED
GP_OUT
Figure 27. TransmittWord Timing Diagram
Cycle0 Cycle1 Cycle2 Cycle3
Test0
Test1
Test2
Test3
D98TL321
MCLK
CLWD
AFRXD
GP_IN(0)
Figure 28. ReceiveWord Timing Diagram
Table 1: Transmitted Bits Assigned to Signal /
Time Slot
Cycle 0
Cycle 1
Cycle 2 Cycle 3
AFTXD[0]
b0
b4
b8
b12
AFTXD[1]
b1
b5
b9
b13
AFTXD[2]
b2
b6
b10
b14
AFTXD[3]
b3
b7
b11
b15
GP_OUT
t0
t1
t2
t3
Table 2: Transmitted Bits Assigned to Signal /
Time Slot
Cycle 0
Cycle 1
Cycle 2 Cycle 3
AFRXD[0]
b0
b4
b8
b12
AFRXD[1]
b1
b5
b9
b13
AFRXD[2]
b2
b6
b10
b14
AFRXD[3]
b3
b7
b11
b15
GP_IN
t0
t1
t2
t3
Tc
Tv
D98TL322
MCLK
CLWD
AFTXD
AFTXED
Figure 29. Transmit Interface
Th
Ts
D98TL323
MCLK
AFRXD
Figure 30. ReceiveInterface
STLC60135
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