74VHC125 datasheet(1/12 Pages) STMICROELECTRONICS

Il numero della parte	74VHC125

Spiegazioni elettronici	QUAD BUS BUFFERS (3-STATE)

PDF	12 Pages

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Produttore elettronici	STMICROELECTRONICS [STMicroelectronics]

Homepage	http://www.st.com

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November 2004

s

HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V

s

LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA=25°C

s

HIGH NOISE IMMUNITY:

VNIH = VNIL = 28% VCC (MIN.)

s

POWER DOWN PROTECTION ON INPUTS

s

SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8mA (MIN)

s

BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s

OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 5.5V

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 125

s

IMPROVED LATCH-UP IMMUNITY

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LOW NOISE: VOLP = 0.8V (MAX.)

DESCRIPTION

The 74VHC125 is an advanced high-speed

CMOS QUAD BUS BUFFERS fabricated with

sub-micron silicon gate and double-layer metal

wiring C2MOS technology.

The device requires the 3-STATE control input G

to be set high to place the output in to the high

impedance state.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74VHC125

QUAD BUS BUFFERS (3-STATE)

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74VHC125MTR

TSSOP

74VHC125TTR

TSSOP

SOP

Rev. 7

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