74VHCT74AMTR datasheet(1/14 Pages) STMICROELECTRONICS

Il numero della parte	74VHCT74AMTR

Spiegazioni elettronici	DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

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Produttore elettronici	STMICROELECTRONICS [STMicroelectronics]

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December 2004

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HIGH SPEED:

fMAX = 160 MHz (TYP.) at VCC = 5V

s

LOW POWER DISSIPATION:

ICC = 2 µA (MAX.) at TA=25°C

s

COMPATIBLE WITH TTL OUTPUTS:

VIH = 2V (MIN.), VIL = 0.8V (MAX)

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POWER DOWN PROTECTION ON INPUTS

& OUTPUTS

s

SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

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BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

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OPERATING VOLTAGE RANGE:

VCC(OPR) = 4.5V to 5.5V

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PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 74

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IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74VHCT74A is an advanced high-speed

CMOS DUAL D-TYPE FLIP FLOP WITH PRESET

AND CLEAR fabricated with sub-micron silicon

gate and double-layer metal wiring C2MOS

technology.

A signal on the D INPUT is transferred to the Q

OUTPUT during the positive going transition of the

clock pulse.

CLR and PR are independent of the clock and

accomplished by a low setting on the appropriate

input.

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage. This

device can be used to interface 5V to 3V since all

inputs are equipped with TTL threshold.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74VHCT74A

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74VHCT74AMTR

TSSOP

74VHCT74ATTR

TSSOP

SOP

Rev. 3

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