LD39150PT18-R datasheet(4/19 Pages) STMICROELECTRONICS

Il numero della parte	LD39150PT18-R

Spiegazioni elettronici	Ultra low drop BICMOS voltage regulator

PDF	19 Pages

Scroll/Zoom	100%

Produttore elettronici	STMICROELECTRONICS [STMicroelectronics]

Homepage	http://www.st.com

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4 / 19 page

Pin configuration

LD39150

4/19

Pin configuration

Figure 2.

Pin connections (top view for DPAK and PPAK, bottom view for DFN)

DFN8 (4x4 mm)

DPAK

PPAK

Table 1.

Pin description

PlN N°

SYMBOL

NOTE

DFN

PPAK

DPAK

VSENSE/N.C.

For fixed versions: to be connected with LDO Output Voltage pins for DFN

package and Not Connected on PPAK

ADJ

For adjustable version: Error Amplifier Input pin for VO from 1.22 to 5.0V

3, 4

LDO Input Voltage; VI from 2.5V to 6V, CI=1µF must be located at a

distance of not more than 0.5’’ from input pin.

6, 7

LDO Output Voltage pins, with minimum CO=2.2µF needed for stability

(also refer to CO vs. ESR stability chart)

VINH

Inhibit Input Voltage: ON MODE when VINH ≥ 2V, OFF MODE when VINH ≤

0.3V (Do not leave floating, not internally pulled down/up)

GND

Common ground

N.C.

Not Connected

LD39150PT18-R Scheda tecnica(PDF) 4 Page - STMicroelectronics