M48Z2M1Y, M48Z2M1V

6/17

READ Mode

The M48Z2M1Y/V is in the READ Mode whenever

W (WRITE Enable) is high and E (Chip Enable) is

low. The device architecture allows ripple-through

access of data from eight of 16,777,216 locations

in the static storage array. Thus, the unique ad-

dress specified by the 21 Address Inputs defines

which one of the 2,097,152 bytes of data is to be

accessed. Valid data will be available at the Data

the last address input signal is stable, providing

that the E (Chip Enable) and G (Output Enable)

access times are also satisfied. If the E and G ac-

cess times are not met, valid data will be available

of the eight three-state Data I/O signals is con-

trolled by E and G. If the outputs are activated be-

puts are changed while E and G remain low, out-

put data will remain valid for Output Data Hold time

dress Access.

Figure 5. Address Controlled, READ Mode AC Waveforms

Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.

Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms

Note: WRITE Enable (W) = High.

AI02051

tAXQX

DATA VALID

A0-A20

DQ0-DQ7

tAVAV

tAVQV

AI02052

tAVAV

tAVQV

tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

DATA OUT

A0-A20

E

G

DQ0-DQ7

VALID