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TDA7505 Scheda tecnica(PDF) 19 Page - STMicroelectronics |
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TDA7505 Scheda tecnica(HTML) 19 Page - STMicroelectronics |
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19 / 38 page ![]() TDA7505 Electrical specifications 19/38 4.6 SAI protocol Figure 5. SAI protocol 4.7 SPDIF receiver Table 12. SAI interface timing - transmitter Timing Description Min Typ Max Unit TDSP (1) 1. TDSP = DSP master clock cycle time = 1/Fdsp Internal DSP clock period (typical 1/75MHz) 13.33 ns tsckt Minimum clock cycle 6 TDSP ns tlrckts LRCKT setup time TDSP ns tlrckth LRCKT hold time TDSP ns tdt SCKT active edge to data out valid TDSP ns tsckth Minimum SCKT high time 0.35 tsckr ns tscktl Minimum SCKT low time 0.35 tsckr ns RIGHT CHANNEL LEFT CHANNEL SDY0-2 LRCKX XREL = 0 XLRS = 0 LRCKX XREL = 0 XLRS = 1 LRCKX XREL = 1 XLRS = 0 15 31 14 30 13 29 0 1 6 5 4 3 2 1 0 15 31 14 30 13 29 6 5 4 3 2 1 0 15 31 14 30 13 29 15 31 14 30 13 29 2 1 0 10 26 11 27 12 28 9 25 15 31 14 30 13 29 2 1 0 10 26 11 27 12 28 9 25 1 0 2 15 31 14 30 SDY0-2 XDIR = 0 XDIR = 1 SCKX SCKX XCKP = 0 XCKP = 1 Notes: 1) X = R for receiver X = T for transmitter 2) Y = I for receiver Y = O for transmitter Table 13. SPDIF receiver Symbol Parameter Test condition Min Typ Max Unit fspdif Input sampling rate Fdsp = 75 MHz 32 96 kHz Input precision with direct interface to DSP 24 bit Input precision with interface to ASRC 20 bit |
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