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M74HC280 Scheda tecnica(PDF) 1 Page - STMicroelectronics |
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M74HC280 Scheda tecnica(HTML) 1 Page - STMicroelectronics |
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1 / 9 page ![]() 1/9 July 2001 s HIGH SPEED : tPD = 22ns (TYP.) at VCC = 6V s LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 280 DESCRIPTION The M74HC280 is an high speed CMOS 9-BIT PARITY GENERATOR fabricated with silicon gate C2MOS technology. It is composed of nine data inputs (A to I) and odd/ even parity outputs ( ΣODD and ΣEVEN). The nine data inputs control the output conditions. When the number of high level input is odd, ΣODD output is kept high and ΣEVEN output low. Conversely, when the output is even, ΣEVEN output is kept high and ΣODD low. The IC generates either odd or even parity making it flexible application. The word-length capability is easily expanded by cascading. All inputs are equipped with protection circuits against static discharge and transient excess voltage. M74HC280 9 BIT PARITY GENERATOR PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP M74HC280B1R SOP M74HC280M1R M74HC280RM13TR TSSOP M74HC280TTR TSSOP DIP SOP |
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Descrizione simile - M74HC280 |
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