PM8800ATR datasheet(22/35 Pages) STMICROELECTRONICS

22 / 35 page

PD interface

PM8800A

22/35

5.7

Power good indication

The PM8800A embeds a power good circuit that is used to indicate that PWM input

capacitors are fully charged and that the switching regulator can start operation. The power

good circuit monitors the status of the internal hot-swap MOSFET and nPGD, an active low

signal is asserted when its VDS voltage falls below 1.5 V and VGS rise above 2 V. The power

good circuit includes hysteresis to allow the PM8800A to operate near the current limit point

without inadvertently disabling nPGD. The MOSFET voltage must increase to 3 V before

nPGD is disabled.

An internal comparator monitors the status of the nPGD pin and the PWM controller will be

running until the voltage at this pin goes above 2 V.

The power good indication is exposed at nPGD pin with a open drain, 45

Ω MOSFET so that

board designers can put a LED and a series current limiting resistor from the VCC pin to the

nPGD pin to indicate that the PD is powered from the PoE network.

Since the power good signal is internally used to activate the PWM controller, to avoid that

transients on the input voltage could produce intermittent operation of the PWM controller,

board designer can connect a capacitor CPGD between the nPGD pin and GND. This will

mask the nPGD signal for a duration that can be estimate by the following equation:

where 30

µA is an internal current source that act as pull-up on the nPGD pin and I

LED is the

current flowing through the external LED, if present.

∆t µs

()

2V C

PGD nF

()

⋅

()

0.03mA

LED mA

()

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