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OR4 Scheda tecnica(PDF) 95 Page - Lattice Semiconductor

Il numero della parte OR4
Spiegazioni elettronici  ORCASeries 4 FPGAs
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OR4 Scheda tecnica(HTML) 95 Page - Lattice Semiconductor

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Lattice Semiconductor
95
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued) 
Table 59. Master Serial Configuration Mode Timing Characteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +125 °C; 
CL =  30 pF.
Note: Serial configuration data is transmitted out on DOUT on the rising edge of CCLK after it is input on DIN.
* Data gets clocked out from an external serial ROM. The clock to data delay of the serial ROM must be less than the CCLK frequency since 
the data available out of the serial ROM must be setup and waiting to be clocked into the FPGA before the next CCLK rising edge.
5-4532(F).b
Figure 54. Master Serial Configuration Mode Timing Diagram
Parameter
Symbol
Min
Max
Unit
DIN Setup Time*
TS
10.00
—
ns
DIN Hold Time
TH
0.00
—
ns
CCLK Frequency (M3 = 0)
FC
5.00
16.67
MHz
CCLK Frequency (M3 = 1)
FC
0.63
2.08
MHz
CCLK to DOUT Delay
TD
—
5.00
ns
DIN
CCLK
DOUT
TS
TH
BIT N
BIT N
TD



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