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STP40NF10L Scheda tecnica(PDF) 3 Page - STMicroelectronics |
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STP40NF10L Scheda tecnica(HTML) 3 Page - STMicroelectronics |
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3 / 8 page ![]() 3/8 STP40NF10L ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time VDD = 50 V, ID = 20 A RG = 4.7Ω VGS = 4.5V (see test circuit, Figure 3) 25 ns tr Rise Time 82 ns Qg Total Gate Charge VDD = 80V, ID =40A,VGS = 5V 46 64 nC Qgs Gate-Source Charge 12 nC Qgd Gate-Drain Charge 22 nC Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf Turn-off-Delay Time Fall Time VDD = 50 V, ID = 20 A, RG =4.7Ω, VGS = 4.5V (see test circuit, Figure 3) 64 24 ns ns td(off) tf tc Off-voltage Rise Time Fall Time Cross-over Time Vclamp =80V, ID = 40 A RG =4.7Ω, VGS = 4.5V (see test circuit, Figure 3) 51 29 53 ns ns ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 40 A ISDM (1) Source-drain Current (pulsed) 160 A VSD (2) Forward On Voltage ISD = 40 A, VGS = 0 1.3 V trr Qrr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, di/dt = 100A/µs, VDD = 30V, Tj = 150°C (see test circuit, Figure 5) 110 467 8 ns nC A Safe Operating Area Thermal Impedance |
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