ST62E03LMASLASHCCCE datasheet(16/96 Pages) STMICROELECTRONICS

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ST6200CM-Auto/ ST6201CM-Auto/ST6203CM-Auto

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4 CENTRAL PROCESSING UNIT

4.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the

I/O or Memory configuration. As such, it may be

thought of as an independent central processor

communicating with on-chip I/O, Memory and Pe-

ripherals via internal address, data, and control

buses.

4.2 MAIN FEATURES

■ 40 basic instructions

■ 9 main addressing modes

■ Two 8-bit index registers

■ Two 8-bit short direct registers

■ Low power modes

■ Maskable hardware interrupts

■ 6-level hardware stack

4.3 CPU REGISTERS

The ST6 Family CPU core features six registers and

three pairs of flags available to the programmer.

These are described in the following paragraphs.

Accumulator (A). The accumulator is an 8-bit

general purpose register used in all arithmetic cal-

culations, logical operations, and data manipula-

tions. The accumulator can be addressed in Data

Space as a RAM location at address FFh. Thus

the ST6 can manipulate the accumulator just like

any other register in Data Space.

Index Registers (X, Y). These two registers are

used in Indirect addressing mode as pointers to

memory locations in Data Space. They can also

be accessed in Direct, Short Direct, or Bit Direct

addressing modes. They are mapped in Data

Space at addresses 80h (X) and 81h (Y) and can

be accessed like any other memory location.

Short Direct Registers (V, W). These two regis-

ters are used in Short Direct addressing mode.

This means that the data stored in V or W can be

accessed with a one-byte instruction (four CPU cy-

cles). V and W can also be accessed using Direct

and Bit Direct addressing modes. They are

mapped in Data Space at addresses 82h (V) and

83h (W) and can be accessed like any other mem-

ory location.

Note: The X and Y registers can also be used as

Short Direct registers in the same way as V and W.

Program Counter (PC). The program counter is a

12-bit register which contains the address of the

next instruction to be executed by the core. This

ROM location may be an opcode, an operand, or

the address of an operand.

Figure 7. CPU Registers

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ 0FFEh-0FFFh

RESET VALUE = xxh

x = Undefined value

V SHORT INDIRECT

RESET VALUE = xxh

W SHORT INDIRECT

RESET VALUE = xxh

NORMAL FLAGS

CNMI ZNMI

INTERRUPT FLAGS

NMI FLAGS

SIX LEVEL

STACK

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