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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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STLS2F02 Scheda tecnica(PDF) 20 Page - STMicroelectronics |
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STLS2F02 Scheda tecnica(HTML) 20 Page - STMicroelectronics |
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20 / 49 page  IO bus interface description STLS2F02 20/49 Figure 6. Local bus write timing 3.6 Interrupt handling An interrupt controller is built into the STLS2F02 processor to handle internal and external interrupt. The 4 most significant bits of the interrupt INTn[5:0] in L2E are still used as interrupts in the STLS2F02, while the other two bits are used for new interrupts, such as PCI_IRQ and GPIO. Interrupt between processors is handled as follows: 1. The interrupt initiator writes the dedicated interrupt register in the chipset. 2. Upon receiving the request for interrupt transmission, the chipset requests the target processor for an interrupt. 3. The processor handles the request in the same way as the previous L2E. lioden liodir lioadlock liocs pciclk lioaddr lioad liowr addr[7:0] addr[7:0]+1 addr[23:8]data_0 data_1 |
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