STPCELITE datasheet(65/87 Pages) STMICROELECTRONICS

65 / 87 page

DESIGN GUIDELINES

Release 1.3 - January 29, 2002

65/87

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

6.3.4. PCI BUS

The PCI bus is always active and the following

control signals must be pulled-up to 3.3V or 5V

through 2K2 resistors even if this bus is not

connected to an external device: FRAME#,

TRDY#, IRDY#, STOP#, DEVSEL#, LOCK#,

SERR#, PCI_REQ#[2:0].

PCI_CLKO must be connected to PCI_CLKI

through a 10 to 33 Ohms resistor. Figure 6-7

shows a typical implementation.

For more information on layout constraints, go to

the place and route recommendations section.

In the case of higher clock load it is recommended

to use a zero-delay clock buffer as described in

Figure 6-8. This approach is also recommended

when

implementing

the

delay

PCICLKI

according to the PCI section of the Electrical

Specifications chapter.

Figure 6-7. Typical PCI clock routing

PCICLKI

PCICLKO

PCICLKA

PCICLKB

PCICLKC

0 - 22

10 - 33

Device A

Device B

Device C

0 - 33pF

Figure 6-8. PCI clock routing with zero-delay clock buffer

PCICLKI

PCICLKO

Device A

Device B

Device C

PLL

Device D

PCICLKI

PCICLKO

Device A

Device B

Device C

PLL

Device D

CY2305

Implementation 1

Implementation 2

STPCELITE Scheda tecnica(PDF) 65 Page - STMicroelectronics

STPCELITE Scheda tecnica(HTML) 65 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

Scheda tecnica Scarica

Link URL