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33911 Scheda tecnica(PDF) 13 Page - Freescale Semiconductor, Inc

Il numero della parte 33911
Spiegazioni elettronici  LIN System Basis Chip with DC Motor Pre-driver
PDF  45 Pages
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Produttore elettronici  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
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33911 Scheda tecnica(HTML) 13 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
13
33911
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5V
≤ V
SUP ≤ 18V, -40°C ≤ TA ≤ 125°C for the 33911 and -40°C ≤ TA ≤ 85°C for the
34911, otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions,
unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE TIMING (see Figure 13, page 19
)
SPI Operating Frequency
fSPIOP
––
4.0
MHz
SCLK Clock Period
tPSCLK
250
N/A
ns
SCLK Clock High Time(42)
tWSCLKH
110
N/A
ns
SCLK Clock Low Time(42)
tWSCLKL
110
N/A
ns
Falling Edge of CS to Rising Edge of SCLK(42)
tLEAD
100
N/A
ns
Falling Edge of SCLK to CS Rising Edge(42)
tLAG
100
N/A
ns
MOSI to Falling Edge of SCLK(42)
tSISU
40
N/A
ns
Falling Edge of SCLK to MOSI(42)
tSIH
40
N/A
ns
MISO Rise Time(42)
CL = 220pF
tRSO
40
ns
MISO Fall Time(42)
CL = 220pF
tFSO
40
ns
Time from Falling or Rising Edges of CS to:(42)
- MISO Low-impedance
- MISO High -impedance
tSOEN
tSODIS
0.0
0.0
50
50
ns
Time from Rising Edge of SCLK to MISO Data Valid(42)
0.2 x VDD ≤ MISO ≥ 0.8 x VDD, CL = 100pF
tVALID
0.0
75
ns
RST OUTPUT PIN
Reset Low-Level Duration after VDD High (see Figure 12, page 19)
tRST
0.65
1.0
1.35
ms
Reset Deglitch Filter Time
tRSTDF
350
600
900
ns
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
Watchdog Time Period (43)
External Resistor REXT = 20kΩ (1%)
External Resistor REXT = 200kΩ (1%)
Without External Resistor REXT (WDCONF pin open)
tPWD
8.5
79
110
10
94
150
11.5
108
205
ms
Notes
42.
This parameter is guaranteed by process monitoring but not production tested.
43.
Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ)



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