R8C datasheet(46/49 Pages) RENESAS

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REVISION HISTORY

R8C/1A Group, R8C/1B Group Datasheet

Rev.

Date

Description

Page

Summary

0.10

Feb 18, 2005

−

First Edition issued

0.20

Jun 01, 2005

2, 3

Tables 1.1, 1.2: Item name changed

Table 1.5: Timer C’s Pin name revised,

Reference Voltage Input Description revised

0.30

Jul 04, 2005

Table 4.1 the value after reset revised;

0009h address “XXXXXX00b”

→ “00h”,

000Ah address “00XXX000b”

→ “00h”,

001Eh address “XXXXX000b”

→ “00h”.

Table 4.2 004Fh address; “SSU/IIC Interrupt Control Register, SSUAIC/

IIC2AIC, XXXXX000b” added

Table 4.3 the value after reset revised;

00BCh address “00h”

→ “00h / 0000X000b”

20 to 39 5. Electrical Characteristics added

1.00

Sep 01, 2005

all pages “Under development” deleted

Table 1.2 Performance Outline of the R8C/1B Group;

Flash Memory:

(Data area)

→ (Data flash)

(Program area)

→ (Program ROM) revised

Figure 1.1 Block Diagram;

“Peripheral Function” added,

“System Clock Generation”

→ “System Clock Generator” revised

Table 1.3 Product Information of R8C/1A Group;

“(D)” and “(D): Under development” deleted

Table 1.4 Product Information of R8C/1B Group;

“(D)” and “(D): Under development” deleted

ROM capacity: (Program area)

→ (Program ROM),

(Data area)

→ (Data flash) revised

Table 1.5 Pin Description;

Power Supply Input: “VCC/AVCC”

→ “VCC”,

“VSS/AVSS”

→ “VSS” revised

Analog Power Supply Input: added

Figure 2.1 CPU Register;

“Reserved Area”

→ “Reserved Bit” revised

2.8.10 Reserved Area;

“Reserved Area”

→ “Reserved Bit” revised

3.2 R8C/1B Group, Figure 3.2 Memory Map of R8C/1B Group;

“Data area”

→ “Data flash”,

“Program area”

→ “Program ROM” revised

R8C/1A Group, R8C/1B Group Datasheet

REVISION HISTORY

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