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HD74LS77FPEL Scheda tecnica(PDF) 1 Page - Renesas Technology Corp |
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HD74LS77FPEL Scheda tecnica(HTML) 1 Page - Renesas Technology Corp |
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1 / 5 page ![]() Rev.3.00, Jul.22.2005, page 1 of 4 HD74LS77 4-bit Bistable Latches REJ03D0418–0300 Rev.3.00 Jul.22.2005 The HD74LS77 is ideally suited for use as temporary storage for binary information between processing units and input / output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go high. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS77FPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP EL (2,000 pcs/reel) Pin Arrangement (Top view) 1Q 2Q Enable 1-2 GND 3Q NC 1D NC 2D Enable 3-4 VCC 3D 4D 4Q 1 2 3 4 5 6 7 14 8 9 10 11 12 13 Q Q G D G D Q G D Q G D Function Table Inputs Outputs D G Q L H L H H H X L Q0 H; high level, L; low level, X; irrelevant |
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