3802 datasheet(39/52 Pages) RENESAS

39 / 52 page

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3802 Group

Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”.

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

INT0 to INT4 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT4 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O2 clock input cycle time

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O2 clock input “H” pulse width

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O2 clock input “L” pulse width

Serial I/O1 input set up time

Serial I/O2 input set up time

Serial I/O1 input hold time

Serial I/O2 input hold time

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twH(INT)

twL(CNTR)

twL(INT)

tc(SCLK1)

tc(SCLK2)

twH(SCLK1)

twH(SCLK2)

twL(SCLK1)

twL(SCLK2)

tsu(RXD–SCLK1)

tsu(SIN2–SCLK2)

th(SCLK1–RXD)

th(SCLK2–SIN2)

Symbol

Parameter

Limits

Min.

µs

Unit

TIMING REQUIREMENTS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85

°C, unless otherwise noted)

125

200

800

1000

370

400

370

400

220

200

100

200

Typ.

Max.

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

INT0 to INT4 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT4 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O2 clock input cycle time

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O2 clock input “H” pulse width

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O2 clock input “L” pulse width

Serial I/O1 input set up time

Serial I/O2 input set up time

Serial I/O1 input hold time

Serial I/O2 input hold time

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twH(INT)

twL(CNTR)

twL(INT)

tc(SCLK1)

tc(SCLK2)

twH(SCLK1)

twH(SCLK2)

twL(SCLK1)

twL(SCLK2)

tsu(RXD–SCLK1)

tsu(SIN2–SCLK2)

th(SCLK1–RXD)

th(SCLK2–SIN2)

Symbol

Parameter

Limits

Min.

µs

Unit

TIMING REQUIREMENTS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85

°C, unless otherwise noted)

500/

(3 VCC–8)

200/

(3 VCC–8)

200/

(3 VCC–8)

500

230

2000

950

400

200

300

Typ.

Max.

Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0”.

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