STV0118 datasheet(32/42 Pages) STMICROELECTRONICS

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VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

VI - REGISTERS (continued)

REGISTER_4 - Configuration4

MSB

LSB

Content

syncin_ad1

syncin_ad0

syncout_ad1 syncout_ad0

aline

txdl2

txdl1

txdl0

Default

syncin_ad

Adjustment of incoming sync signals (Refer to Functional Description, Section IV.5).

Used to insure correct interpretation of incoming video samples as Y, Cr or Cb when the

encoderis slaved to incoming sync signals (incl. ‘F/H’ flags stripped offITU-R656/D1 data).

syncin_ad1

syncin_ad0

Internal delay undergone by incoming sync

(*)

Nominal

+1 ckref

+2 ckref

+3 ckref

syncout_ad Adjustment of outgoing sync signals (Refer to Functional Description, SectionIV.4).

Used to insure correct interpretation of incoming video samples as Y, Cr or Cb when the

encoder is master and supplies sync signals.

syncout_ad1 syncout_ad0 Delay added to sync signals before they are output

(*)

Nominal

+1 ckref

+2 ckref

+3 ckref

aline

Video active line duration control(Refer to Functional Description, Section IV.2)

(*)

Full digital video line encoding (720 pixels - 1440 clock cycles)

Active line duration follows ITU-R/SMPTE ‘analog’ standard requirements

txdl[2:0]

Teletext data latency (* “000” default) (Refer to Functional Description, Section IV.15)

The encoder will clock in the first Teletext data sample on the (2+txdl[2:0])

th rising edge

of the master clock following the rising edge of TTXS (Teletext Synchro signal, supplied

by the encoder).

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