STV0299B datasheet(9/36 Pages) STMICROELECTRONICS

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STV0299B

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FUNCTIONAL DESCRIPTION (continued)

Figure 4:

Clock Signal Generation

Note:

Refer to the Register List P[2:0] in table 1

At the rising edge of RESET signal (pin 15) the corresponding bit of the I2C bus register is forced to the status of pin STDBY or

to DIRCLK-DIS.

Table 1:

Divider Programming

Table 2:

Summary of FM_CLK

LPF

VCO

1/4

1/16

÷R

1/2

PHASE

COMPARATOR

÷(M+1)

1/6

TO SERIAL

SHIFTER

÷(K+1)

OSC

÷P(Note 1)

STDBY

DiSEqC/tone

burst modulator

1/0

PROGRAMABLE

DIVIDER

DIRCLK-CTRL

1/0

XTAL OUT

XTAL IN/CLK-IN

DIRCLK-DIS

F22/

DiSEqCTM

AUX_CLK

M_CLK

Note 2

VCO

ON/OFF

Note 2

VCO ON/OFF

STDBY

(I2C bit)

I2C

DIRCLK (I2C bit)

I2C

Reg 01[4:0]

Reg 01[7:6]

Reg 02[2:0]

Reg 08[2:0]

Reg 04

Reg 03

PRESCALER

1/2

K(1:0) in register

fREF = fXTAL divided by:

M(4:0) in register

fVCO = fREF

multiplied by:

00000

00001

00010

00011

...

11111

128

P(2:0) in register

fM_CLK = fVCO

divided by P:

000

001

010

011

100

101

110

111

DIRCLK_CTRL = 0

DIRCLK_CTRL =1

STDBY = 1

VCO

XTAL

--------------

⋅

M_CLK

VCO

------------

M_CLK

CLK_IN

M_CLK

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