STV9427 datasheet(13/20 Pages) STMICROELECTRONICS

13 / 20 page

FUNCTIONAL DESCRIPTION (continued)

HSYNC

R, G, B

LD[6:1] = 40

DD[7:0] = 10

Nber of characters

of the row

16 780 81

6.5

Active OSD Video

Figure 7 : Hozizontal Timing

IV - Clock and Timing

The whole timing is derived from the XTI and the

horizontal SYNCHRO input frequencies. The XTI

input frequency can be an external clock, crystal

or a ceramic resonator signal thanks to XTI/XTO

pins. The value of this frequency can be chosen

between 6 and 15MHz is used by the PLL to

generate a pixel clock locked on the horizontal

synchro input signal.

IV.1 - Horizontal Timing (see Figure 7)

The number of pixel periods is given by the LINE

DURATION register and is equal to :

[LD[6:1] x 2 + 1 ] x 12.

(LD[6:1] : value of the LINE DURATION register).

This value allows to define the horizontal size of the

characters.

The horizontal left margin is given by the HORI-

ZONTAL DELAY register and is equal to :

(DD[7:0] -6 ) x 6 + 54

(DD[7:0] : value of the DISPLAY DELAY register).

This value allows to define the horizontal position

of the characters on the screen. Due to internal

logic, minimum horizontal delay is fixed at 4.5

characters (54 pixel) when DD is even and lower

or equal to 6, and it is fixed at 5 characters (60 pixel)

when DD is odd and lower or equal to 7.

IV.2 - D to A Timing (STV9427)

The D/A converters of the STV9427 are pulse width

modulator converter.

The frequency of the output signal is :

fXTAL

256

x 6

and

the duty cycle is :

Vi[7:0]

256 x 6

per cent.

After a low pass filter, the average value of the

output is :

Vi [7:0]

256 x 6

⋅ VDD

V - Display Control

A screen is composed of successive scanlines gath-

ered in several strips. Each strip is defined by a

descriptor stored in memory. A table of descriptors

allows screen composition and different tables can

be stored in memory at the page addresses

(16 possible

≠ addresses). Two types of strips are

available :

- Spacing strip : its descriptor (see II) gives the

number of black (FBK = 1 in DISPLAY CONTROL

- Character strip : its descriptor gives the memory

address of the character codes corresponding to

the 1

st displayed character. The characters and

attributes (see code format III) are defined by a

succession of codes stored in the RAM at ad-

dresses starting from the 1

st one given by the

descriptor. A character strip can be displayed or

not by using the DE bit of its descriptor.

After the VSYNC edge, the first strip descriptor is

read at the top of the current table of descriptors at

the address given by P[9:0] (see DISPLAY CON-

TROL register) ; if it is a spacing strip, SL[7:0] black

or transparent scan lines are displayed ; if it is a

character strip, during CH[5:0] scan lines (CH[5:0]

given by the CHARACTER HEIGHT register), the

character codes are read at the addresses starting

from the 1

st one given by the descriptor until a end

of line character or the end of the scan line ; the

next descriptor is then read and the same process

is repeated until the next edge of VSYNC.

128

255

V1[7:0]

TXTAL

256 . TXTAL

PWM1 Signal

Figure 8 : PWM Timing

STV9427 - STV9428 - STV9429

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