M5M5V216ATP,RT

revision-03, 14.Jan.'03

2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI LSIs

6

Note 3: Hatching indicates the state is "don't care".

Note 4: A Write occurs during S low , ov erlaps BC1 and/or BC2 low and W low.

Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.

Note 5: When the f alling edge of W is simultaneously or priorto the f alling edge of BC1 and/or BC2 or the f alling edge of S,

W

Write cycle (BC control mode)

DATA IN

STABLE

(Note3)

(Note3)

(Note4)

(Note5)

W

S

Write cycle (S control mode)

DATA IN

STABLE

(Note3)

(Note3)

(Note4)

(Note5)

(Note3)

(Note3)

S

BC1

BC2

and / or

(Note3)

(Note3)

(Note4)

BC1

BC2

and / or

the outputs are maintained in the high impedance state.