R5S72011 datasheet(13/1196 Pages) RENESAS

13 / 1196 page

Rev. 2.00 Sep. 07, 2007 Page xiii of xxviii

7.3.4

Break Data Mask Register (BDMR) ..................................................................... 167

7.3.5

Break Bus Cycle Register (BBR).......................................................................... 168

7.3.6

Break Control Register (BRCR) ........................................................................... 170

7.4

Operation ........................................................................................................................... 173

7.4.1

Flow of the User Break Operation ........................................................................ 173

7.4.2

Break on Instruction Fetch Cycle.......................................................................... 174

7.4.3

Break on Data Access Cycle................................................................................. 175

7.4.4

Value of Saved Program Counter ......................................................................... 176

7.4.5

Usage Examples.................................................................................................... 177

7.5

Usage Notes ....................................................................................................................... 180

Section 8 Cache .................................................................................................183

8.1

Features.............................................................................................................................. 183

8.1.1

Cache Structure..................................................................................................... 183

8.2

Register Descriptions ......................................................................................................... 186

8.2.1

Cache Control Register 1 (CCR1) ........................................................................ 186

8.2.2

Cache Control Register 2 (CCR2) ........................................................................ 188

8.3

Operation ........................................................................................................................... 191

8.3.1

Searching Cache ................................................................................................... 191

8.3.2

Read Access.......................................................................................................... 193

8.3.3

Prefetch Operation (Only for Operand Cache) ..................................................... 193

8.3.4

Write Operation (Only for Operand Cache).......................................................... 193

8.3.5

Write-Back Buffer (Only for Operand Cache)...................................................... 194

8.3.6

Coherency of Cache and External Memory .......................................................... 196

8.4

Memory-Mapped Cache .................................................................................................... 196

8.4.1

Address Array ....................................................................................................... 196

8.4.2

Data Array ............................................................................................................ 197

8.4.3

Usage Examples.................................................................................................... 199

8.4.4

Notes ..................................................................................................................... 200

Section 9 Bus State Controller (BSC)................................................................201

9.1

Features.............................................................................................................................. 201

9.2

Input/Output Pins ...............................................................................................................203

9.3

Area Overview ...................................................................................................................205

9.3.1

Address Map ......................................................................................................... 205

9.3.2

Data Bus Width and Pin Function Setting for Individual Areas ........................... 206

9.4

Register Descriptions ......................................................................................................... 207

9.4.1

CSn Control Register (CSnCNT) (n = 0 to 6)....................................................... 209

9.4.2

CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 6) ............................. 211

9.4.3

SDRAMCm Control Register (SDCmCNT) (m = 0, 1)........................................ 213

R5S72011 Scheda tecnica(PDF) 13 Page - Renesas Technology Corp

R5S72011 Scheda tecnica(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL