M16CSLASH29 datasheet(458/499 Pages) RENESAS

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22. Usage Notes

page 434

6. When a count is started and the first effective edge is input, an undefined value is transferred to the

reload register. At this time, timer Bi interrupt request is not generated.

7. A value of the counter is undefined at the beginning of a count. MR3 may be set to 1 and timer Bi

interrupt request may be generated between a count start and an effective edge input.

8. For pulse width measurement, pulse widths are successively measured. Use program to check

whether the measurement result is an “H” level width or an “L” level width.

22.6.3 Three-phase Motor Control Timer Function

When the IVPCR1 bit in the TB2SC register is set to 1 (three-phase output forced cutoff by SD pin input

(high-impedance) enabled), the INV03 bit in the INVC0 register is set to 1 (three-phase motor control

_____

timer output enabled), and a low-level ("L") signal is applied to the SD pin while a three-phase PWM

___

signal is output, the MCU is forced to cutoff and pins U, U, V, V, W, and W are placed in a high-impedance

state and the INV03 bit is set to 0 (three-phase motor control timer output disabled).

___

To resume the three-phase PWM signal output from pins U, U, V, V, W, and W, set the INV03 bit to 1 and

_____

the IVPCR1 bit to 0 (three-phase output forced cutoff disabled) after the SD pin level becomes "H". Then

set the IVPCR1 bit to 1 (three-phase output forced cutoff enabled) in order to enable the three-phase

output forced cutoff function by input to the SD pin again.

_____

The INV03 bit cannot be set to 1 while an "L" signal is input to the SD pin. To set the INV03 bit to 1 after

forcible cutoff, write 1 to the INV03 bit and read the bit to ensure that it is set to 1 by program. Then set the

IVPCR1 bit to 1 after setting it to 0.

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