38K2 datasheet(14/358 Pages) RENESAS

14 / 358 page

Rev.2.00

Oct 15, 2006

page 10 of 14

38K2 Group

REJ09B0338-0200

List of figures

Fig. 3.1.3 SB output switching characteristics measurement circuit (2) for D0+, D1+/D2+ (full-speed),

D1-/D2- (low-speed) ...... 13

Fig. 3.1.4 Timing chart (1) ............................................................................................................. 14

Fig. 3.1.5 Timing chart (2) ............................................................................................................. 15

Fig. 3.1.6 Timing chart (3) ............................................................................................................. 16

Fig. 3.1.7 Timing chart (4) ............................................................................................................. 17

Fig. 3.1.8 Timing chart (5) ............................................................................................................. 18

Fig. 3.1.9 Timing chart (6) ............................................................................................................. 19

Fig. 3.2.1 Sequence of changing relevant register .................................................................... 22

Fig. 3.2.2 Sequence of check of interrupt request bit ............................................................... 23

Fig. 3.2.3 Sequence of setting serial I/O control register again .............................................. 25

Fig. 3.2.4 Initialization of processor status register ................................................................... 29

Fig. 3.2.5 Sequence of PLP instruction execution ..................................................................... 29

Fig. 3.2.6 Stack memory contents after PHP instruction execution ........................................ 29

Fig. 3.2.7 Status flag at decimal calculations ............................................................................. 30

Fig. 3.3.1 Selection of packages .................................................................................................. 32

_____________

Fig. 3.3.2 Wiring for the RESET pin ............................................................................................ 32

Fig. 3.3.3 Wiring for clock I/O pins .............................................................................................. 33

Fig. 3.3.4 Wiring for CNVSS pin ..................................................................................................... 33

Fig. 3.3.5 Wiring for the VPP pin of the flash memory version ................................................. 34

Fig. 3.3.6 Bypass capacitor across the VSS line and the VCC line ........................................... 34

Fig. 3.3.7 Analog signal line and a resistor and a capacitor ................................................... 35

Fig. 3.3.8 Wiring for a large current signal line ......................................................................... 36

___________

Fig. 3.3.9 Wiring of RESET pin .................................................................................................... 36

Fig. 3.3.10 VSS pattern on the underside of an oscillator ......................................................... 37

Fig. 3.3.11 Setup for I/O ports ...................................................................................................... 37

Fig. 3.3.12 Watchdog timer by software ...................................................................................... 38

Fig. 3.4.1 Structure of Port Pi ....................................................................................................... 39

Fig. 3.4.2 Structure of Port Pi direction register ........................................................................ 39

Fig. 3.4.3 Structure of USB control register ................................................................................ 40

Fig. 3.4.4 Structure of USB function/HUB enable register ........................................................ 40

Fig. 3.4.5 Structure of USB function address register ............................................................... 40

Fig. 3.4.6 Structure of USB HUB address register .................................................................... 41

Fig. 3.4.7 Structure of Frame number register Low ................................................................... 41

Fig. 3.4.8 Structure of Frame number register High .................................................................. 41

Fig. 3.4.9 Structure of USB interrupt source enable register ................................................... 41

Fig. 3.4.10 Structure of USB interrupt source register .............................................................. 42

Fig. 3.4.11 Structure of Endpoint index register ......................................................................... 42

Fig. 3.4.12 Structure of EP00 stage register .............................................................................. 43

Fig. 3.4.13 Structure of EP01 set register .................................................................................. 43

Fig. 3.4.14 Structure of EP02 set register .................................................................................. 44

Fig. 3.4.15 Structure of EP03 set register .................................................................................. 44

Fig. 3.4.16 Structure of EP10 stage register .............................................................................. 45

Fig. 3.4.17 Structure of EP11 set register .................................................................................. 45

Fig. 3.4.18 Structure of EP00 control register 1 ........................................................................ 45

Fig. 3.4.19 Structure of EP01 control register 1 ........................................................................ 46

Fig. 3.4.20 Structure of EP02 control register 1 ........................................................................ 46

Fig. 3.4.21 Structure of EP03 control register 1 ........................................................................ 46

Fig. 3.4.22 Structure of EP10 control register 1 ........................................................................ 47

Fig. 3.4.23 Structure of EP11 control register 1 ........................................................................ 47

Fig. 3.4.24 Structure of EP00 control register 2 ........................................................................ 47

Fig. 3.4.25 Structure of EP01 control register 2 ........................................................................ 48

Fig. 3.4.26 Structure of EP02 control register 2 ........................................................................ 48

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