H8SSLASH2223 datasheet(221/1071 Pages) RENESAS

221 / 1071 page

Section 5 Interrupt Controller

Rev. 5.00 Aug 08, 2006 page 135 of 982

REJ09B0054-0500

5.4

Interrupt Sources

5.4.1

External Interrupts

There are nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore

this LSI from software standby mode.

NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU

regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG

bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling

edge on the NMI pin.

IRQn Interrupts (n = 7 to 0): IRQn interrupts are requested by an input signal at

IRQn pins.

IRQn interrupts have the following features:

• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling

edge, rising edge, or both edges, at

IRQn pins.

• Enabling or disabling of IRQn interrupt requests can be selected with IER.

• The interrupt priority level can be set with IPR.

• The status of IRQn interrupt requests is indicated in ISR. ISR flags can be cleared to 0 by

software.

A block diagram of IRQn interrupts is shown in figure 5.2.

IRQnE

IRQnF

IRQn interrupt

request

Clear signal

Edge/level

detection circuit

IRQnSCA, IRQnSCB

IRQn input

Note: n = 7 to 0

Figure 5.2 Block Diagram of IRQn Interrupts

The set timing for IRQnF is shown in figure 5.3.

H8S/2223 Scheda tecnica(PDF) 221 Page - Renesas Technology Corp