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SH7014 Scheda tecnica(PDF) 156 Page - Renesas Technology Corp

Il numero della parte SH7014
Spiegazioni elettronici  32-Bit RISC Microcomputer
PDF  754 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7014 Scheda tecnica(HTML) 156 Page - Renesas Technology Corp

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8. Bus State Controller (BSC)
Rev.5.00 Sep. 27, 2007 Page 122 of 716
REJ09B0398-0500
8.2.8
Refresh Time Constant Register (RTCOR)
RTCOR is a 16-bit read/write register that establishes the compare match period with RTCNT.
The values of RTCOR and RTCNT are constantly compared. When the values correspond, the
compare match flag of RTCSR is set and RTCNT is cleared to 0.
When the refresh bit (RFSH) of the RTCSR is set to 1 and the RMD bit is 0, a refresh request
signal is produced by this match. The refresh request signal is held until a refresh operation is
performed. If the refresh request is not processed before the next match, the previous request
becomes ineffective.
When the CMIE bit of the RTSCR is set to 1, an interrupt request is sent to the interrupt controller
by this match signal. The interrupt request is output continuously until the CMF bit of the RTSCR
is cleared.
Bits 15 to 8 are reserved and cannot be used in setting the period. They always read 0.
RTCOR is initialized by power-on resets to H'0000, but is not initialized by software standbys.
Bit:
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W



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