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HD6433637SW Scheda tecnica(PDF) 37 Page - Renesas Technology Corp |
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HD6433637SW Scheda tecnica(HTML) 37 Page - Renesas Technology Corp |
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37 / 418 page ![]() 23 Table 2.2 Effective Address Calculation No. Addressing Mode and Instruction Format Effective Address Calculation Method Effective Address (EA) 1 Register direct, Rn Operand is contents of registers indicated by rm/rn op rm rn 87 3 40 15 rm 30 rn 30 2 op rm 76 3 40 15 Register indirect, @Rn Contents (16 bits) of register indicated by rm 0 15 0 15 3 Register indirect with displacement, @(d:16, Rn) op rm 76 3 40 15 disp 0 15 disp 0 15 Contents (16 bits) of register indicated by rm 4 op rm 76 3 40 15 Register indirect with post-increment, @Rn+ op rm 76 3 40 15 Register indirect with pre-decrement, @–Rn Incremented or decremented by 1 if operand is byte size, and by 2 if word size 0 15 1 or 2 0 15 0 15 1 or 2 0 15 Contents (16 bits) of register indicated by rm Contents (16 bits) of register indicated by rm |
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