HD6433636SW datasheet(341/418 Pages) RENESAS

341 / 418 page

327

A.3

Number of Execution States

The following describes the operation status in each instruction provided for the H8/300 L CPU,

as well as a calculation of the number of execution states. Table A.4 gives the number of cycles

(as the operation status) for such operations as an instruction fetch, data read/write performed

during an instruction execution. Table A.3 gives the number of execution states required for each

cycle (operation status). The total number of states required for the execution of an instruction can

be calculated by using the following equation:

Execution states = I

× S

I + J × S J + K × S K + L × S L + M × S M + N × S N

Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.

1. BSET #0, @FF00

From table A.4:

I = L = 2,

J = K = M = N= 0

From table A.3:

I = 2,

L = 2

Number of states required for execution = 2

× 2 + 2 × 2 = 8

When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM,

and on-chip RAM is used for stack area.

2. JSR @@ 30

From table A.4:

I = 2,

J = K = 1,

L = M = N = 0

From table A.3:

I = SJ = SK = 2

Number of states required for execution = 2

× 2 + 1 × 2+ 1 × 2 = 8

HD6433636SW Scheda tecnica(PDF) 341 Page - Renesas Technology Corp