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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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HD6433636SW Scheda tecnica(PDF) 194 Page - Renesas Technology Corp |
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HD6433636SW Scheda tecnica(HTML) 194 Page - Renesas Technology Corp |
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194 / 418 page  180 TCF Count Timing: TCF is incremented by each pulse of the input clock (internal clock or external event). • Internal clock The settings of bits CKSH2 to CKSH0 or bits CKSL2 to CKSL0 in TCRF select one of four internal clock signals (ø/32, ø/16, ø/4, or ø/2) divided from the system clock (ø). • External event External event input is selected by clearing bit CKSL2 to 0 in TCRF. Either rising or falling edges of the clock input can be counted. The edge is selected by bit IEG3 in IEGR. An external clock pulse width of at least two system clock cycles (ø) is necessary; otherwise the counter will not operate properly. TMOFH and TMOFL Output Timing: The outputs at pins TMOFH and TMOFL are the values set in bits TOLH and TOLL in TCRF. When a compare match occurs, the output value is inverted. Figure 9.5 shows the output timing. ø TMIF (when IEG3 = 1) Count input clock TCF OCRF Compare match signal TMOFH, TMOFL N N + 1 N N + 1 NN Figure 9.5 TMOFH, TMOFL Output Timing TCF Clear Timing: TCF can be cleared at compare match with OCRF. Timer Overflow Flag (OVF) Set Timing: OVF is set to 1 when TCF overflows (goes from H'FFFF to H'0000). |
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