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SH7018 Scheda tecnica(PDF) 77 Page - Renesas Technology Corp |
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SH7018 Scheda tecnica(HTML) 77 Page - Renesas Technology Corp |
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77 / 431 page ![]() 61 6.1.3 Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Abbreviation I/O Function Non-maskable interrupt input pin NMI I Input of non-maskable interrupt request signal Interrupt request input pins IRQ0 to IRQ3, IRQ6, IRQ7 I Input of maskable interrupt request signals 6.1.4 Register Configuration The INTC has the 10 registers shown in table 6.2. These registers set the priority of the interrupts and control external interrupt input signal detection. Table 6.2 Register Configuration Name Abbr. R/W Initial Value Address Access Sizes Interrupt priority register A IPRA R/W H'0000 H'FFFF8348 8, 16, 32 Interrupt priority register B IPRB R/W H'0000 H'FFFF834A 8, 16, 32 Interrupt priority register C IPRC R/W H'0000 H'FFFF834C 8, 16, 32 Interrupt priority register D IPRD R/W H'0000 H'FFFF834E 8, 16, 32 Interrupt priority register E IPRE R/W H'0000 H'FFFF8350 8, 16, 32 Interrupt priority register F IPRF R/W H'0000 H'FFFF8352 8, 16, 32 Interrupt priority register G IPRG R/W H'0000 H'FFFF8354 8, 16, 32 Interrupt priority register H IPRH R/W H'0000 H'FFFF8356 8, 16, 32 Interrupt control register ICR R/W *1 H'FFFF8358 8, 16, 32 IRQ status register ISR R(W)* 2 H'0000 H'FFFF835A 8, 16, 32 Notes: 1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000. 2. Only 0 can be written, in order to clear flags. |
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