SH7052 datasheet(460/919 Pages) RENESAS

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13.3.2

CMCNT Count Timing

One of four clocks (P

φ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral clock (Pφ)

can be selected by the CKS1 and CKS0 bits of CMCSR. Figure 13.3 shows the timing.

N – 1

N + 1

Internal clock

CMCNT input

clock

CMCNT

Figure 13.3 Count Timing

13.4

Interrupts

13.4.1

Interrupt Sources and DTC Activation

The CMT has a compare match interrupt for each channel, with independent vector addresses

allocated to each of them. The corresponding interrupt request is output when interrupt request

flag CMF is set to 1 and interrupt enable bit CMIE has also been set to 1.

When activating CPU interrupts by interrupt request, the priority between the channels can be

changed by means of interrupt controller settings. See section 6, Interrupt Controller, for details.

13.4.2

Compare Match Flag Set Timing

The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the

CMCOR register and the CMCNT counter match. The compare match signal is generated upon

the final state of the match (timing at which the CMCNT counter matching count value is

updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare

match signal will not be generated until a CMCNT counter input clock occurs. Figure 13.4 shows

the CMF bit set timing.

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