SH7052 datasheet(98/919 Pages) RENESAS

Il numero della parte	SH7052

Spiegazioni elettronici	SuperHTM RISC engine

PDF	919 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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5.6

When Exception Sources Are Not Accepted

When an address error or interrupt is generated after a delayed branch instruction or interrupt-

disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in

table 5.10. When this happens, it will be accepted when an instruction that can accept the

exception is decoded.

Table 5.10

Generation of Exception Sources Immediately after a Delayed Branch

Instruction or Interrupt-Disabled Instruction

Exception Source

Point of Occurrence

Bus Error

Interrupt

FPU Exception

Immediately after a delayed branch

instruction*

Not accepted

Immediately after an interrupt-disabled

instruction*

Not accepted*

Not accepted

Accepted

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF

2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L

3. In the SH-2 a bus error is accepted.

SH7052 Scheda tecnica(PDF) 98 Page - Renesas Technology Corp