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SH7713 Scheda tecnica(PDF) 152 Page - Renesas Technology Corp

Il numero della parte SH7713
Spiegazioni elettronici  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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Section 3 DSP Operating Unit
Rev.1.50 Aug. 30, 2006 Page 112 of 860
REJ09B0288-0150
Table 3.17
DSP Operation Instruction Formats
Type
Instruction Formats
Double data operation instructions
ALUop. Sx, Sy, Du
MLTop. Se, Df, Dg
Conditional single data operation
instructions
DCT
ALUop. Sx, Sy, Dz
DCF
ALUop. Sx, Sy, Dz
DCT
ALUop. Sx, Dz
DCF
ALUop. Sx, Dz
DCT
ALUop. Sy, Dz
DCF
ALUop. Sy, Dz
Unconditional single data operation
instructions
ALUop. Sx, Sy, Dz
ALUop. Sx, Dz
ALUop. Sy, Dz
MLTop. Se, Sf, Dg
Table 3.18
Correspondence between DSP Instruction Operands and Registers
ALU/Shift Operations
Multiply Operations
Register
Sx
Sy
Dz
Du
Se
Sf
Dg
A0
Yes
Yes
Yes
Yes
A1
Yes
Yes
Yes
Yes
Yes
Yes
M0
Yes
Yes
Yes
M1
Yes
Yes
Yes
X0
Yes
Yes
Yes
Yes
Yes
X1
Yes
Yes
Yes
Y0
Yes
Yes
Yes
Yes
Yes
Y1
Yes
Yes
Yes
When writing parallel instructions, the B-field instruction is written first, followed by the A-field
instruction. A sample parallel processing program is shown in figure 3.6.



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